- 您现在的位置：买卖IC网 > Sheet目录1220 > IP-SDRAM/DDR2 (Altera)IP DDR2 SDRAM CONTROLLER
3–4
1
f
Chapter 3: Functional Description
Device-Level Description
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior
of the other megafunctions.
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
For more information on OpenCore Plus hardware evaluation, refer to “OpenCore
Device-Level Description
This section describes the following topics:
■
■
■
■
■
Datapath
In Stratix series, the DDR and DDR2 SDRAM controllers use input-output element
(IOE) registers in the write and the read direction. In the read direction, the phase
shift reference circuit provides a process, voltage, temperature (PVT) compensated
delay on each DQS that is used to sample the DQ read data. In Cyclone series, the
DDR SDRAM controller uses carefully placed logic element (LE) registers to
guarantee consistent timing across DQS groups. An appropriate DQS delay is
produced by the Cyclone series programmable delay, the value of which is set by the
constraints script.
In the read direction, the double-rate data from the DQ pins are fed into positive and
a negative edge-triggered registers to sample data on both edges of DQS. These
signals are then passed through another set of configurable registers to return them to
the system clock domain. The IP Toolbench timing analysis configures the transition
from the DQS clock domain to the system clock domain (resynchronization). The
options range from using the positive edge of the system clock as your
resynchronization clock to more complex cases that require one or more extra sets of
registers to safely return your read data to the system clock domain.
f
For more information on resynchronization, refer to “Resynchronization” on
? March 2009 Altera Corporation
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
IP-SLITE2
IP SERIALLITE II
IP-SRAM/QDRII
IP QDRII SRAM CONTROLLER
IP-VITERBI/SS
IP VITERBI LOW-SPEED
IP4220CZ6,125
IC USB DUAL ESD PROTECT 6TSOP
IPA-66-1-600-10.0-A-01-T
CIRC BRKR 10A 2POLE SCREW TERM
IPR-CSC
IP COLOR SPACE CONVERTER RENEW
IPR-ED8B10B
IP 8B10B ENCODER/DECODER RENEW
IPS-VIDEO
IP VIDEO/IMAGE PROCESSING SUITE
相关代理商/技术参数
IP-SDRAM/DDR3
功能描述:开发软件 DDR3 SDRAM Control MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR
功能描述:开发软件 DDR SDRAM Control MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR2
功能描述:开发软件 DDR2 SDRAM Control MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/LPDDR2
功能描述:开发软件 DDR2 SDRAM Control MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPSE.4.33SM600
制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50)
IPSE.4.62SM600
制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50)
IPS-EMBEDDED
功能描述:开发软件 Embedded IP Suite MegaCore
RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPS-EVAL-EH-01
功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP